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Genuine Motorola 68882 Math CoProcessor PGA 25mhz, BRAND NEW, MC68882RC25A
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Genuine Motorola 68882 Math CoProcessor PGA 25mhz, BRAND NEW, MC68882RC25A
Price: US $36.50
Appearance: NEW OLD STOCK, slight wear
Description:============Similar to pictured, a Motorola 68882 math co-processor: MC68882RC25A.
Warranty and Returns:=====================We understand that there may be compatibility issues, space constraints, or it just doesn’t look perfect. This item can be returned within 14-days for ANY reason. However, shipping to and from is not refundable.
Shipping:=========- Local pickup is also available at no cost.- Most orders placed before 9am will ship the same day.
About Us:=========The Computer Preservation Group is dedicated to the preservation of historical computers. To help fund ongoing operations, select items are made available. To learn more, please visit our website. Thank you for your from wikipedia:
The Motorola 68881 and Motorola 68882 were floating-point coprocessor (FPU) devices that were used in some computer systems in conjunction with the 68020 or 68030 microprocessors. The addition of one of these devices added substantial cost to the computer, but added a floating point unit that could rapidly perform floating point mathematical calculations. At the time[when?], this feature was useful mostly for scientific and mathematical software.
OverviewA Motorola 68882 FPUThe 68020 and 68030 CPUs were designed with the separate 68881 chip in mind. Their instruction sets reserved the "F-line" instructions — that is, all opcodes beginning with the hexadecimal digit "F" could either be forwarded to an external coprocessor or be used as "traps" which would throw an exception, handing control to the computer's operating system. If an FPU is not present in the system, the OS would then either call an FPU emulator to execute the instruction's equivalent using 68020 integer-based software code, return an error to the program, terminate the program, or crash and require a reboot.
ArchitectureThe 68881 had eight 80-bit data registers[1][2] (a 64-bit mantissa plus a sign bit, and a 15-bit signed exponent). It allowed seven different modes of numeric representation, including single-precision, double-precision, and extended-precision, as defined by the IEEE floating-point standard, IEEE 754. It was designed specifically for floating-point math and was not a general-purpose CPU. For example, when an instruction required any address calculations, the main CPU would handle them before the 68881 took control.
The CPU/FPU pair were designed such that both could run at the same time. When the CPU encountered a 68881 instruction, it would hand the FPU all operands needed for that instruction, and then the FPU would release the CPU to go on and execute the next instruction.

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